"Og" <Og@yahoo.com> wrote in message
news:OApBql7AIHA.4444@TK2MSFTNGP03.phx.gbl...
> "Fazal" <Fazal@discussions.microsoft.com> wrote in message
> news:683727EA-947A-43FD-B3A5-90CF97C0C5DE@microsoft.com...
>> The reason I ask this question is because about 3-4 years ago I was
>> listening
>> to Scott Mueller (popular computer technician) who was explaning how RAM
>> works. He said that the L1 cache runs at about same speed as the
>> microprocessor and Intel claims to have a 9/10 'cache hit ratio'. If a
>> 'cache
>> miss' occurs then the L2 cache also has a 9/10 'cache hit ratio.' He said
>> only if a cache miss occurs on both the L1 and L2 cache will the physical
>> RAM
>> will be accessed (which ofcourse is a slower process). Therefore he
>> reasoned
>> that if we add more RAM you will only be increasing your performance 1%
>> of
>> the time. And this is why RAM speeds today are so much slower than CPU
>> speeds; they simply have no reason to keep up.
>> I was just wondering how logical is this arguement and is it the truth?
>>
>> Thank you
>
> I suspect that you have mis-understood Scott Mueller. You seem to be
> comparing ham-hocks to beans; they are two completely different foods
> that, taken together, perform an olfactory feat that neither food can
> obtain independently of the other.
>
> *CACHE* memory [L1 and, if a processor has it, L2] serves an entirely
> different function than *Random Access Memory* (RAM) serves.
>
> CACHE memory exists to store snippets of "action" code (VERB) that the
> processor will soon use, or that will be reused multiple times in a
> sequence of calculations.
> RAM stores not just snippets of code, but entire programs of code (both
> NOUN and VERB).
>
> Think of yourself as a "computer", think of RAM as your office, and think
> of CACHE memory a workspace where you use each of the individual tools
> within your office. From your writing class you have 100 vocabulary words
> that you must discover definitions for. From your math class you have 100
> equations upon which you must perform a Laplace Transform.
> You (the processor) decide to do your vocabulary first, so you "pre-fetch"
> a dictionary and place it in the CACHE (your desk). With your tool place
> in CACHE, you do not need to get up from your desk and retrieve a
> dictionary 100 times for 100 words -- you use, 100 times, the dictionary
> that is placed in your CACHE.
> Having completed your vocabulary assignment, you discard the dictionary
> from CACHE and replace it with a calculator -- you use, 100 times, the
> calculator.
>
That is a bit of a complicated explanation, though not inaccurate.
It would be quite possible to connect RAM memory to the CPU that is capable
of operating at the speed the CPU would expect it to. Such memory (known as
static memory) is relatively complicated, physically large and very, very,
expensive. However, it would not require any additional cache, and would
make for a very fast, but very expensive PC.
In practice, a compromise is made and the type of RAM fitted is dynamic
memory, which is relatively simple, small, cheap and slow. Its only
disadvantage is that this latter memory will only remember data for a few
milliseconds so it has to be constantly refreshed. This is all taken care
of in the memory chips themselves these days and so does not actually pose
any problems.
In order to speed up operations, when a memory access is made, that chunk of
memory is copied into a faster L2 cache. In turn a smaller chunk is copied
into an even faster L1 cache. The processor can now access the L1 cache at
full speed. As other chunks are required they are copied as required. This
provides a substantial speed advantage than if there were no cache, but is
not as fast as the first scheme. The caches are made from expensive static
RAM, but are universally built into the processor itself these days.
The process can be reversed if a memory write takes place, but the actual
write back to the L2 cache and then to the dynamic RAM is delayed until it
has to occur or after a suitable time interval. Motherboards can be
configured to perform the write back to the dynamic RAM immediatley.