In the PCI Local Bus Specification / Revision: 2.2 / December 18, 1998 I found the following:
PCI-2.2, page 114:
PCI components on the Universal board must use I/O buffers that can be compliant with either the 5V or 3,3 V signaling environment. While there are multiple buffer implementations that can achieve this dual environment compliance, it is intended that they be dual voltage buffers; i. e., capable of operating from either power rail. They should be powered from “I/O” designated power pins [27] on PCI connectors that will always be connected to the power rail associated with the signaling environment in use. This means that in the 5V signaling environment, these buffers are powered on the 5V rail. When the same board is plugged into a 3,3V connector, these buffers are powered on the 3,3V rail. This enables the Universal Board to be compliant with either signaling environment.
The intent of this transition approach is to move 5V component technology into the 3,3V signaling environment, rather than forcing 3,3V component technology to operate in a 5V signaling environment. While the later can be done, it is more difficult and more expensive, especially in an unterminated, modular bus environment. The preferred alternative – moving 5V components into a 3,3 V signaling environment – can be done without any incremental cost, and has, in addition, some signal performance benefits.
All new component designs are recommended to use the dual voltage buffers. All new expansion boards are recommended to be Universal boards. This allows expansion boards based on 5V component technology to be used in both 5V and 3,3V systems, thus enabling the move to 3,3V systems.
[27]: While the primary goal of the PCI 5V to 3,3V transition strategy is to spare vendors the burden and expense of implementing 3,3V parts that are “5V tolerant”, such parts are not excluded. If a PCI component of this type is used on the Universal board, its I/O buffers may optionally be connected to the “I/O” designated power pins; but high clamp diodes must still be connected to the “I/O” designated power pins. (Refer to the last paragraph of Section 4.2.1.2. – “Clamping directly to the 3,3V rail with a simple diode must never be used in the 5V signaling environment.”) Since the effective operation of these high clamp diodes may be critical to both signal quality and device reliability, the designer must provide enough extra “I/O” designated power pins on a component to handle the current spikes associated with the 5V maximum AC waveforms (Section 4.2.1.3.).
3,3V Operating Voltage with 5V tolerant I/O just means that such a chip could be used to for the 3,3V signaling environment as well as for the 5V signaling environment.
